1. Field
Various embodiments of the present invention relate to a semiconductor design technology and, more particularly, to a semiconductor device, a semiconductor system with the semiconductor device and a method of driving the semiconductor system.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional semiconductor system.
Referring to FIG. 1, the conventional semiconductor system includes a control device 10 and first to eighth semiconductor devices 20A to 20H. The control device 10 generates a clock signal CLK, command signals CMDs, address signals ADDRs, first to eighth data strobe signals DQS0 to DQS7 and first to eighth data signals DQ0 to DQ7. The first to eighth semiconductor devices 20A to 20H perform predetermined operations based on the dock signal CLK, the command signals CMDs, the address signals ADDRs, the first to eighth data strobe signals DQS0 to DQS7 and the first to eighth data signals DQ0 to DQ7. The first to eighth semiconductor devices 20A to 20H share the clock signal CLK, the command signals CMDs, and the address signals ADDRs, and separately receive the respective first to eighth data strobe signals DQS0 to DQS7 and the respective first to eighth data signals DQ0 to DQ7.
The control device 10 controls the predetermined operations of the first to eighth semiconductor devices 20A to 20H. For example, the control device 10 controls refresh operations and data input/output operations of the first to eighth semiconductor devices 20A to 20H. For reference, a refresh operation denotes an operation in which memory cells included in a semiconductor device are read and updated (or rewritten) with amplified data.
The first to eighth semiconductor devices 20A to 20H perform the predetermined operations under the control of the control device 10. For example, the first to eighth semiconductor devices 20A to 20H perform the refresh operations at the same time in response to the clock signal CLK and the command signals CMDs and individually perform the data input/output operations in response to the clock signal CLK, the command signals CMDs, the address signals ADDRs, the respective data strobe signals DQS0 to DQS7 and the respective data signals DQ0 to DQ7.
FIG. 2 is a timing diagram for describing an operation of the conventional semiconductor system shown in FIG. 1.
Referring to FIG. 2, the control device 10 sequentially generates the command signals CMDs corresponding to a refresh command signal REF at a predetermined cycle. Then, the first to eighth semiconductor devices 20A to 20H perform the refresh operations at the same time whenever the refresh command signal REF is applied. This causes considerable current consumption in the first to eighth semiconductor devices 20A to 20H, and the current consumption results in power noise. The more semiconductor devices included in the semiconductor system, the more serious the power noise becomes. In other words, as the density of integration of the semiconductor devices increases the power noise may become a more serious concern.
Therefore, technology for decreasing the power noise occurring when the first to eighth semiconductor devices 20A to 20H simultaneously perform the refresh operations is in demand.